CPU Pipelining

What is CPU Pipelining?

Is the process of accumulating instruction from the processor through a pipeline. It allows storing and executing instructions in an orderly process. It is known as pipeline processing. In simple terms breaking down the job into smaller parts. Also, it is a special technique to increase processor performance.

Pipelining breaks instruction execution down into several stages:

— Put registers between stages to “buffer” data and control

— Execute one instruction

— As first starts the second stage, execute second instruction, etc.

— Speedup same as a number of stages as long as the pipe is full.

6 stages of instructions in the CPU pipelining:

Stage 01:

• Fetch Instruction (FI): Read the next instruction into the buffer.

Stage 02:

• Decode Instruction (DI): Determine the opcode.

Stage 03:

• Calculate operands (FO): Fetch each operand from memory.

Stage 04:

• Fetch operand (FO): Fetch each operand from memory.

Stage 05 :

• Execute instruction(EI): Perform the indicated operation.

Stage 06:

• Write operand (WO): Store the result in memory.

Pipeline Hazards

• Pipeline hazards are situations that prevent the next instruction in the instruction stream from executing during its designated clock cycles.
• Any condition that causes a stall in the pipeline operations can be called a hazard.
• There are primarily three types of hazards:

i. Data Hazards

ii. Control Hazards (instruction Hazards)

iii. Structural Hazards.

Data Hazards:

A data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline. As a result of which some operation has to be delayed and the pipeline stalls. Whenever there are two instructions one of which depends on the data obtained from the other.

A=3+A | B=A*4

For the above sequence, the second instruction needs the value of ‘A’ computed in the first instruction.

Thus the second instruction is said to depend on the first.

If the execution is done in a pipelined processor, it is highly likely that the interleaving of these two instructions can lead to incorrect results due to data dependency between the instructions. Thus the pipeline needs to be stalled as and when necessary to avoid errors.

Control hazards:

The instruction fetch unit of the CPU is responsible for providing a stream of instructions to the execution unit. The instructions fetched by the fetch unit are in consecutive memory locations and they are executed.

However, the problem arises when one of the instructions is a branching instruction to some other memory location. Thus all the instructions fetched in the pipeline from consecutive memory locations are invalid now and need to removed(also called flushing of the pipeline). This induces a stall till new instructions are again fetched from the memory address specified in the branch instruction.

Structural Hazards:

This situation arises mainly when two instructions require a given hardware resource at the same time and hence for one of the instructions the pipeline needs to be stalled.

The most common case is when memory is accessed at the same time by two instructions. One instruction may need to access the memory as part of the Execute or Write back phase while other instruction is being fetched. In this case, if both the instructions and data reside in the same memory. Both the instructions can’t proceed together and one of them needs to be stalled till the other is done with the memory access part. Thus in general sufficient hardware resources are needed for avoiding structural hazards.

Resource Hazards

Two or more instructions in the pipeline need the same resource. Executed in serial rather than parallel for part of the pipeline. Also called a structural hazard. The ideal case is new instruction enters the pipeline each clock cycle. Here we assume that the main memory has a single port. And also instruction fetches and data reads and writes performed one at a time. In resource, hazards ignore the cache. Operand read or write can't be performed in parallel with instruction fetch. In resource hazards when two or more instructions in the pipeline need the same resource. here the instructions must be executed in serial for a portion of the pipeline.

Hope you found interesting facts. !!!!!! :)